Want to go to Disney World in January 2019? #MK365

Are you interested in learning how technology is driving brand loyalty at Walt Disney World? Explore mobile applications, RFID, and social media integration on campus in the fall. Explore Walt Disney World in-person through testing family itineraries, backstage tours, and yes… plenty of fun! Talk to Dr. Carrie Trimble or me to learn more. Consider taking MK365, Brand Loyalty Experience, as part of your fall 2018 schedule. Watch the video below to learn more.

 

I.S. Tech Night – Wed. 10/25 6-8pm

I.S. Tech Night
When: Wednesday, October 25 – 6:00pm – 8:00pm
Where: University Commons 138
What Else: Yes, there will be pizza and snacks

  •  Are you an undecided business major or exploratory studies?
  • Do you like robots?
  • Are you curious about what jobs are available for information systems (I.S.) majors?
  • Do you like free pizza?
  • Are you currently an I.S. major, math major, or pursuing an I.S. certificate?

If you answered yes to at least one of the above questions, join us for a fun night of playing with robotic cars, learning about information systems (I.S.) programs and MU Performance Consulting (student-run venture), and also hear about other student projects.

So we can plan on enough food, please RSVP to either RJ Podeschi or Ed Weber by Tuesday, October 24th.

We hope you can join us,

RJ Podeschi and Ed Weber

Student-run Venture Career Fair on 11/1

November 1st 2017 4-6pm in the University Commons 140, 142, 150, 152 

Why do we need a Student Venture Career Fair?

  1. Students that are required to take a student venture often don’t know all the options they have. This will bring awareness so they can pick one that they are passionate about or they think they can make the most difference.
  2. Ventures often get students through telling their friends to join the class. This would provide ventures with a more diverse student pool and increase visibility.
  3. This is a good opportunity for potential students to visit and see yet another layer of what Millikin has to offer.

Student Ventures to be involved:

  1. Blue Brew Coffee Shop
  2. Big Blue Personal Training
  3. Blue Connection Retail Art Gallery
  4. Blue Satellite Press
  5. Bronze Man Books Publishing Company
  6. Carriage House Press
  7. First Step Records
  8. Ignite Studios Ad Agency and Gaphic Design Firm
  9. MUPC IT Consulting
  10. Pipe Dreams Studio Theatre

RISC vs. CISC & Processor Architecture #IS311

cpuTwo philosophies have driven the design of microprocessors. One perspective uses complex instruction set computing (CISC) which deliberately includes complex instructions. This methodology allows for simpler machine-language programs at the expense of adding additional control unit circuitry (Burd, 2016, p. 120). Leading chip manufacturers such as Intel and AMD have placed more emphasis on increasing processor speed to accommodate for the extra instruction cycles. The contrasting school of thought uses a reduced instruction set computing (RISC) methodology. These processors avoid instructions that combine data transformation and data movement operations. RISC processors have the advantage of being the processor architecture of choice for computationally intensive applications. These two opposing architectures have been in existence over the past 50 years mostly for backwards compatibility purposes. Intel processors include approximately 678 different instruction sets and the chip manufacturer must be able to provide backward compatibility for programs written on older platforms (Burd, 2016, p. 134). Because of RISC’s simpler instruction set design, it is believed that these processors use less power than CISC and are optimal for battery-powered and low-power devices (Clark, 2013). Blem, Menon, and Sankaralingam compared these two architectures and found that neither processor specification was more energy efficient than the other (2013). Although two different processor design methodologies continue to be prevalent in the marketplace, there doesn’t appear to be an emerging leader in the near future.

Cache Memory

While processor speed and performance continues to be an important factor in system architecture, the CPU will continue to need efficient ways of accessing data for input, processing, and output. The CPU has an integrated set of methods to take advantage of its multiple cores and high clock speeds. For example, the use of cache memory, a special storage area (usually RAM) can be used to improve system performance. Although volatile, cache can use algorithms to predict what data is used most frequently from secondary storage. Because primary memory is usually limited in storage capacity and more expensive, secondary storage in the form of magnetic media is most often used to store files such as databases, video, and program files. Magnetic media uses multiple platters that spin on a servo motor to be accessed by a read/write head. As a result, it takes time for the CPU to request that data through device controllers and eventually locate the data on the physical disk. In relational database management systems like Oracle, for example, using cache algorithms can significantly reduce query times for processing and reporting.

Chip architecture, cache, and secondary storage are all interrelated when considering design choices for system architecture. The available technology, performance implications, interoperability, and future technology all affect system performance. In the past 10 years, multi-core processors have changed the way data center managers think about virtualization technology to reduce server sprawl and increase server utilization percentage. However, this technology wouldn’t have come to fruition if processor designers hadn’t run up against the “power wall” by continuing to increase clock speed (Venu, 2011). Quantum computing continues to be researched so that, eventually, it can scale to become more affordable. Storage technology is now being thought about in the same vein as researchers are trying to write data at the atomic level on copper sheets using chlorine at sub-zero temperatures (The Economist, 2016). The innovators and engineers will continue to rethink our preconceived notion to allow for faster processing and higher storage capacities to meet the demands of the marketplace.

References

Atoms and the voids. (2016, July 23). The Economist (US)

Blem, E., Menon, J., & Sankaralingam, K. (2013). Power struggles: Revisiting the RISC vs. CISC debate on contemporary ARM and x86 architectures. Proceedings – International Symposium on High-Performance Computer Architecture, (Hpca), 1–12. https://doi.org/10.1109/HPCA.2013.6522302

Burd, S.D. (2016). Systems Architecture 7e. Boston, MA: Cengage Learning

Clark, J. (2013, April 09). ARM Versus Intel: Instant Replay of RISC Versus CISC. Retrieved September 17, 2016, from http://www.datacenterjournal.com/arm-intel-instant-replay-risc-cisc/

Venu, B. (2011). Multi-core processors-An overview. arXiv Preprint arXiv:1110.3535. Retrieved from http://arxiv.org/abs/1110.3535

What I.S. Projects Do You Want to ShowCase? #TaborPerforms

Applications are now being accepted for
Celebrations of Scholarship/Poster Symposium Day
Friday, April 28, 2017.

The eighth annual Celebrations of Scholarship will showcase the outstanding work of Millikin students. During this celebratory event, students will present the results of their research, scholarship, and creative efforts to the Millikin community.
In addition, the Annual Research Poster Symposium will highlight the scholarly work completed by students.

The application for Celebrations of Scholarship is available at: https://www.millikin.edu/webform/celebrations-scholarship

FINAL DEADLINE for submission will be March 10, 2017

The application for Poster Symposium is available at: https://www.millikin.edu/cos-poster-symposium

FINAL DEADLINE for submission will be April 3, 2017

NO APPLICATIONS WILL BE ACCEPTED AFTER THE FINAL DEADLINE

Questions regarding application or submission may be directed to Lori Gilbert and Kathy Housh at celebrationsofscholarship@millikin.edu