Happy FFFing Friday Series, 2/17 @ 9am

Take part in stimulating discussions and hear real stories that prove why failure can be the stepping stone to success. We will hear from a seasoned entrepreneur, every week, who will give an honest testimonial about the hardships they encountered on their way to success and the lessons learned that got them through.

The Happy FFFing Friday series will be February 17th from 9:00 a.m. to 10:00 a.m. in ADM Scovill Room 107. 

Jesse Reising is Co-Founder and former Board Chairman and President of the Warrior-Scholar Project (warrior-scholar.org), a nonprofit organization that hosts “academic boot camps” at over a dozen universities nationwide to help veterans transition from the military to college. After graduating from Decatur Eisenhower High School, Jesse attended and played football at Yale University and planned to join the Marine Corps after he graduated. In the final moments of his last football game, the 2010 Yale-Harvard Game, he was involved in a devastating collision that injured his neck and left parts of his right arm paralyzed. Unable to join the Marine Corps, Jesse started the Warrior-Scholar Project to serve those serving in the military in his place. Since the Warrior-Scholar Project’s founding in 2012, they have raised over $4 million and served over 500 veterans.

Jesse will speak about strategies for overcoming the challenges associated with starting and growing a business from the perspective of a social entrepreneur.


Please contact Court Tulak at the Center for Entrepreneurship (ctulak@millikin.edu) with any questions and we look forward to seeing you soon!

I.S. Opportunities – Week of 2/13 #MillikinIS

Digital Trends We Love for 2017 Webinar, Thurs. Feb 16 – 1pm – 2pm – FREE

It’s that time of year when our Brand, Creative, Strategy and Technology teams start to geek out about all the latest trends. And there’s a lot to be excited about. From new 3D web technologies and flexible layouts to video, interactive data visualization and virtual reality, there are so many ways to delight users in 2017.
Join Nate Denton and Jessica DeJong as they share the trends that are exciting them in 2017 (a bit of a digital show and tell, if you will). They’ll touch on the trends that are here to stay, the ones you can leave behind, and even the ones you should be looking forward to in the future. To register, https://goo.gl/vVqDgp

Nerdery Overnight Website Challenge, March 18-19

The Nerdery Overnight Website Challenge is a volunteer-driven program of the Nerdery Foundation, aimed at maximizing the community impact of nonprofit organizations through digital strategy and custom software design and development – all pro bono.
Registration is open now for Chicagoland volunteer web pros and nonprofits vying for their professional services. The sooner you complete your application, the better your odds to get involved – and get the most out of this experience. I haven’t checked to see if they are open to accepting “down-staters,” but it’s worth a short. If interested, register here by February 20: http://chi2017.overnightwebsitechallenge.com/

State Farm Visit Day on Friday, March 31: Save the Date

Tentatively, State Farm will be hosting Millkin at their south campus in Bloomington for a tour of their systems departments, data center, and to interact with alums working at State Farm. More info to come. For now, save the date. More details to come.

ISCPA CareerFest in Tinley Park on Wednesday, Feb 15 – 10am – 3pm – You can sign up at the door on Wednesday

Over 100 employers. If you are a senior and are still looking for employment after graduation, YOU NEED TO GO TO THIS.
Transportation provided by Career Center
A list of employers, many of which are tech-related: https://www.collegecentral.com/CCNEngine/LiveEvents/LiveEvents.cfm?EventID=2249

Midwest Digital Marketing Conference, April 12 and 13 in St. Louis, Union Station

There is an opportunity to hear from some of the best and brightest at companies like Facebook, Google, Salesforce, and Twitter at this year’s Midwest Digital Marketing Conference. It’s hosted by University of Missouri–St. Louis and includes a networking/career fair. To learn more:  https://umsldigitalconference.com/
  • April 12 & 13, 2017
  • Registration for students is $50
If this interests you, please fill out the short form linked here: https://goo.gl/forms/bXReh3pE3Gslr5Hl1
Once we know who is interested, more information will be sent from Dr. Carrie Trimble.

REU Interdisciplinary Research Experience in Computational Sciences

The Center for Computation & Technology (CCT) hosts a ten week Research Experiences for Undergraduates (REU) program where students work collaboratively on a wide variety of computational science projects. Each student receives a stipend of $5,000, free housing in university dormitories, and up to $600 in travel expenses to and from Baton Rouge, Louisiana.  Ten students will be selected.
Undergraduate, community college student, or high school senior attending college in the fall, interested in a major that is within the computational sciences umbrella (leaves out few majors as it includes all sciences, mathematics, engineering, finance, statistics, etc.) with at least a 2.75 GPA, considering a career in research and/or graduate school in your major, being a US citizen or permanent resident, and graduating at least one semester after completion of the REU.
Important Dates:
March 1, 2017: Application deadline.
April 1, 2017: Notification of decision.
May 22, 2017 through July 30, 2017: Program dates.
The research activities of the CCT are organized into five Focus Areas: Core Computing Sciences, Coast to Cosmos, Material World, Cultural Computing, and System Science and Engineering. These are broad, and sometimes overlapping areas where faculty from diverse departments (Mathematics, Computer Science, Physics, Civil Engineering, Oceanography and Coastal Sciences, Petroleum Engineering, Mechanical Engineering, Electrical and Computing Engineering, Music, Business, etc.) collaborate in multidisciplinary projects. Our REU students learn how to use some of the nation’s largest supercomputers, may participate in the setup and management of large-scale simulations, and may take on an important role in the analysis and visualization of the simulation results.
For more information and to apply, visit:  http://reu.cct.lsu.edu/

RISC vs. CISC & Processor Architecture #IS311

cpuTwo philosophies have driven the design of microprocessors. One perspective uses complex instruction set computing (CISC) which deliberately includes complex instructions. This methodology allows for simpler machine-language programs at the expense of adding additional control unit circuitry (Burd, 2016, p. 120). Leading chip manufacturers such as Intel and AMD have placed more emphasis on increasing processor speed to accommodate for the extra instruction cycles. The contrasting school of thought uses a reduced instruction set computing (RISC) methodology. These processors avoid instructions that combine data transformation and data movement operations. RISC processors have the advantage of being the processor architecture of choice for computationally intensive applications. These two opposing architectures have been in existence over the past 50 years mostly for backwards compatibility purposes. Intel processors include approximately 678 different instruction sets and the chip manufacturer must be able to provide backward compatibility for programs written on older platforms (Burd, 2016, p. 134). Because of RISC’s simpler instruction set design, it is believed that these processors use less power than CISC and are optimal for battery-powered and low-power devices (Clark, 2013). Blem, Menon, and Sankaralingam compared these two architectures and found that neither processor specification was more energy efficient than the other (2013). Although two different processor design methodologies continue to be prevalent in the marketplace, there doesn’t appear to be an emerging leader in the near future.

Cache Memory

While processor speed and performance continues to be an important factor in system architecture, the CPU will continue to need efficient ways of accessing data for input, processing, and output. The CPU has an integrated set of methods to take advantage of its multiple cores and high clock speeds. For example, the use of cache memory, a special storage area (usually RAM) can be used to improve system performance. Although volatile, cache can use algorithms to predict what data is used most frequently from secondary storage. Because primary memory is usually limited in storage capacity and more expensive, secondary storage in the form of magnetic media is most often used to store files such as databases, video, and program files. Magnetic media uses multiple platters that spin on a servo motor to be accessed by a read/write head. As a result, it takes time for the CPU to request that data through device controllers and eventually locate the data on the physical disk. In relational database management systems like Oracle, for example, using cache algorithms can significantly reduce query times for processing and reporting.

Chip architecture, cache, and secondary storage are all interrelated when considering design choices for system architecture. The available technology, performance implications, interoperability, and future technology all affect system performance. In the past 10 years, multi-core processors have changed the way data center managers think about virtualization technology to reduce server sprawl and increase server utilization percentage. However, this technology wouldn’t have come to fruition if processor designers hadn’t run up against the “power wall” by continuing to increase clock speed (Venu, 2011). Quantum computing continues to be researched so that, eventually, it can scale to become more affordable. Storage technology is now being thought about in the same vein as researchers are trying to write data at the atomic level on copper sheets using chlorine at sub-zero temperatures (The Economist, 2016). The innovators and engineers will continue to rethink our preconceived notion to allow for faster processing and higher storage capacities to meet the demands of the marketplace.


Atoms and the voids. (2016, July 23). The Economist (US)

Blem, E., Menon, J., & Sankaralingam, K. (2013). Power struggles: Revisiting the RISC vs. CISC debate on contemporary ARM and x86 architectures. Proceedings – International Symposium on High-Performance Computer Architecture, (Hpca), 1–12. https://doi.org/10.1109/HPCA.2013.6522302

Burd, S.D. (2016). Systems Architecture 7e. Boston, MA: Cengage Learning

Clark, J. (2013, April 09). ARM Versus Intel: Instant Replay of RISC Versus CISC. Retrieved September 17, 2016, from http://www.datacenterjournal.com/arm-intel-instant-replay-risc-cisc/

Venu, B. (2011). Multi-core processors-An overview. arXiv Preprint arXiv:1110.3535. Retrieved from http://arxiv.org/abs/1110.3535

What I.S. Projects Do You Want to ShowCase? #TaborPerforms

Applications are now being accepted for
Celebrations of Scholarship/Poster Symposium Day
Friday, April 28, 2017.

The eighth annual Celebrations of Scholarship will showcase the outstanding work of Millikin students. During this celebratory event, students will present the results of their research, scholarship, and creative efforts to the Millikin community.
In addition, the Annual Research Poster Symposium will highlight the scholarly work completed by students.

The application for Celebrations of Scholarship is available at: https://www.millikin.edu/webform/celebrations-scholarship

FINAL DEADLINE for submission will be March 10, 2017

The application for Poster Symposium is available at: https://www.millikin.edu/cos-poster-symposium

FINAL DEADLINE for submission will be April 3, 2017


Questions regarding application or submission may be directed to Lori Gilbert and Kathy Housh at celebrationsofscholarship@millikin.edu


Moore’s Law and Today’s Technology #IS311

The ability to capture, process, store, and present information is faster and less expensive today than it was 50 years ago. Gordon Moore, an engineer at Intel, predicted in 1965 that computing would dramatically increase in power while decreasing in relative cost, roughly every two years (Intel, n.d.). According to a recent article in The Economist, this maxim has stood the test of time over the past 50 years. However, the traditional method of shrinking the size of the transistor to pack more of them onto a processor is reaching its fundamental limit (2016). This technical limit has led engineers to move beyond the principles of classical physics which rely on mathematical rules by using clearly defined binary physical states (Burd, 2016, p. 24). In order to continue to improve processing capabilities, quantum physics is being used by combining classical physics with matter at the subatomic level such that matter can be in multiple states at the same time in a qubit (Burd, 2016, p. 24-25). This nascent technology is still being prototyped, and is far too expensive to hit the public market at this time.

As new architectures for computing are developed, engineers will need to pay particular attention to memory addressing. Today’s Intel processors maintain backwards compatibility for the original 8086 microprocessor which makes it difficult to process an increasing number of bits using faster methodologies (Burd, 2016, p 89-90). This was evidenced at the turn of the millennium when larger computer classes began using 64-bit addressing. The change in architecture caused software compatibility issues despite Intel providing memory addressing based on either 32-bit or 64-bit addressing.

While new advances in processor technology are developed, the average citizen has access to a wide array of consumer electronics that rely upon the classical processor. These microcomputer devices can include smartphones, tablets, e-readers, laptops, and desktop computers. These devices typically support tasks such as browsing the web, creating documents, editing spreadsheets, curating photos, using apps (or applications), or performing business functions using accounting software packages (Burd, 2016, 35). This class of computers sometimes challenges the definition of a workstation which it commonly referred to as a more powerful desktop computer. Workstations are often found in use for applications that require additional primary memory (RAM) for simultaneously running programs, graphics capabilities for applications such as AutoCAD, or multiple CPUs for statisticians who require faster processing capabilities. It may be argued, in support of Moore’s Law, that the capabilities of a workstation may resemble the specifications of the next generation of desktops.

Even though it may be easy for an average consumer to purchase off-the-shelf computing devices for casual personal use, it requires deep technical understanding of the technology to implement, test, and deploy systems for use in the enterprise. Understanding how these components interoperate is critical to a project’s success. In order to manage computing resources effectively, one must stay abreast of future technology trends through unbiased sources, such as those from professional organizations that are funded by memberships rather than specific vendors (Burd, 2016, 8-9).


50 Years of Moore’s Law. (n.d.) Retrieved September 12, 2016, from http://www.intel.com/content/www/us/en/silicon-innovations/moores-law-technology.html#

Burd, S.D. (2016). Systems Architecture 7e. Boston, MA: Cengage Learning

Double, Double, Toil and Trouble. (2016, March 12). The Economist (US)