Two philosophies have driven the design of microprocessors. One perspective uses complex instruction set computing (CISC) which deliberately includes complex instructions. This methodology allows for simpler machine-language programs at the expense of adding additional control unit circuitry (Burd, 2016, p. 120). Leading chip manufacturers such as Intel and AMD have placed more emphasis on increasing processor speed to accommodate for the extra instruction cycles. The contrasting school of thought uses a reduced instruction set computing (RISC) methodology. These processors avoid instructions that combine data transformation and data movement operations. RISC processors have the advantage of being the processor architecture of choice for computationally intensive applications. These two opposing architectures have been in existence over the past 50 years mostly for backwards compatibility purposes. Intel processors include approximately 678 different instruction sets and the chip manufacturer must be able to provide backward compatibility for programs written on older platforms (Burd, 2016, p. 134). Because of RISC’s simpler instruction set design, it is believed that these processors use less power than CISC and are optimal for battery-powered and low-power devices (Clark, 2013). Blem, Menon, and Sankaralingam compared these two architectures and found that neither processor specification was more energy efficient than the other (2013). Although two different processor design methodologies continue to be prevalent in the marketplace, there doesn’t appear to be an emerging leader in the near future.
Cache Memory
While processor speed and performance continues to be an important factor in system architecture, the CPU will continue to need efficient ways of accessing data for input, processing, and output. The CPU has an integrated set of methods to take advantage of its multiple cores and high clock speeds. For example, the use of cache memory, a special storage area (usually RAM) can be used to improve system performance. Although volatile, cache can use algorithms to predict what data is used most frequently from secondary storage. Because primary memory is usually limited in storage capacity and more expensive, secondary storage in the form of magnetic media is most often used to store files such as databases, video, and program files. Magnetic media uses multiple platters that spin on a servo motor to be accessed by a read/write head. As a result, it takes time for the CPU to request that data through device controllers and eventually locate the data on the physical disk. In relational database management systems like Oracle, for example, using cache algorithms can significantly reduce query times for processing and reporting.
Chip architecture, cache, and secondary storage are all interrelated when considering design choices for system architecture. The available technology, performance implications, interoperability, and future technology all affect system performance. In the past 10 years, multi-core processors have changed the way data center managers think about virtualization technology to reduce server sprawl and increase server utilization percentage. However, this technology wouldn’t have come to fruition if processor designers hadn’t run up against the “power wall” by continuing to increase clock speed (Venu, 2011). Quantum computing continues to be researched so that, eventually, it can scale to become more affordable. Storage technology is now being thought about in the same vein as researchers are trying to write data at the atomic level on copper sheets using chlorine at sub-zero temperatures (The Economist, 2016). The innovators and engineers will continue to rethink our preconceived notion to allow for faster processing and higher storage capacities to meet the demands of the marketplace.
References
Atoms and the voids. (2016, July 23). The Economist (US)
Blem, E., Menon, J., & Sankaralingam, K. (2013). Power struggles: Revisiting the RISC vs. CISC debate on contemporary ARM and x86 architectures. Proceedings – International Symposium on High-Performance Computer Architecture, (Hpca), 1–12. https://doi.org/10.1109/HPCA.2013.6522302
Burd, S.D. (2016). Systems Architecture 7e. Boston, MA: Cengage Learning
Clark, J. (2013, April 09). ARM Versus Intel: Instant Replay of RISC Versus CISC. Retrieved September 17, 2016, from http://www.datacenterjournal.com/arm-intel-instant-replay-risc-cisc/
Venu, B. (2011). Multi-core processors-An overview. arXiv Preprint arXiv:1110.3535. Retrieved from http://arxiv.org/abs/1110.3535
